Tiny Energy‐Harvesting Piezoelectric Chargers
This tutorial will be presented in-person ONLY.
Abstract: Wireless microsensors and other miniaturized electronics cannot only monitor and better‐manage power consumption in emerging small‐ and large‐scale applications (for space, military, medical, agricultural, and consumer markets) but also add energy‐saving and performance‐enhancing intelligence to old, expensive, and difficult‐to‐replace infrastructures and tiny contraptions in difficult‐to‐reach places (like the human body). The energy these smart devices store, however, is often insufficient to power the functions they incorporate (such as telemetry, interface, processing, and others) for extended periods. Still more, replacing or recharging the batteries of hundreds of networked nodes is costly, and invasive in the case of the human body. Harvesting ambient kinetic energy in motion to continually replenish a battery is therefore an appealing alternative, even if relevant technologies are still the subject of ardent research today. This talk illustrates, assesses, and compares the state of the art in miniaturized piezoelectric chargers that draw kinetic energy from motion to charge a battery.
Prof Gabriel A. Rincón-Mora
Georgia Institute of Technology
Bio: Gabriel A. Rincón-Mora is Motorola Solutions Foundation Professor at the Georgia Institute of Technology (Georgia Tech), Fellow of the National Academy of Inventors (NAI), Fellow of the Institute of Electrical and Electronics Engineers (IEEE), and Fellow of the Institution of Engineering and Technology (IET). He’s been at Georgia Tech since 2001, was Visiting Professor at National Cheng Kung University in 2011–2019, and was Design Team Leader at Texas Instruments in 1994–2003. He was inducted into Georgia Tech’s Council of Outstanding Young Engineering Alumni, named one of “The 100 Most Influential Hispanics” by Hispanic Business magazine, and included in “List of Notable Venezuelan Americans” in Science. Other distinctions include the National Hispanic in Technology Award, Charles E. Perry Visionary Award, Three-Year Patent Award, Orgullo Hispano Award, Hispanic Heritage Award, State of California Commendation Certificate, and IEEE Distinguished Lecturer. His body of work includes 11 books, 8 handbooks, 4 book chapters, 42 patents, over 190 articles, 25 educational videos, over 26 commercial power-chip products, and over 150 keynotes/speeches/seminars. URL: rincon-mora.gatech.edu.
EDA Tools for Physical Design - Fundamentals and Challenges
Abstract: The development of any integrated circuit depends heavily on the quality of the EDA tools used in the design flow. Improved CAD tools and algorithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this tutorial, we will start by giving an overview of the importance of automation in the design process. Then some trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Basic and advanced optimization algorithms will be presented for selected physical design problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, specially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. A set of tools and algorithms for cell generation will be briefly discussed. Finally, the use of estimation and visualization tools is equally important. They can be applied either in the design flow or just in the tool’s development and research environments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks. Keywords: EDA, VLSI Design, Physical Design, Optimization, Cell Synthesis, Placement, Routing
Prof Ricardo Reis
Federal University of Rio Grande do Sul
Bio: Ricardo Reis received a Bachelor’s degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. Advisor at the Graduate Program on Microelectronics at UFRGS, as well of the Graduate Program on Computing, also at UFRGS. He has been the advisor of more than 100 graduate students. His primary research includes physical design automation, design methodologies, fault tolerant systems, and microelectronics education. He has more than 800 publications, including books, journals, and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing), and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS, and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which received the World CASS Chapter of The Year Award in 2011, 2012, 2018, and 2022, and R9 Chapter of The Year in 2013, 2014, 2016, 2017, and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5, and Chair of IFIP TC10. He also started with the EMicro, an annual microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also a founding member of SBMicro (Brazilian Microelectronics Society). Also, founder of the IEEE CEDA Brazil Chapter. He was a member of IEEE CASS DLP Program (2014/2015), and he has done more than 80 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. He is also a member of the IEEE IoT Initiative Activity Board, representing IEEE CASS. Ricardo is chair of the CASS SiG on IoT. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022.
Prof Marcelo Johann
Federal University of Rio Grande do Sul
Bio: Marcelo Johann (Member of IEEE, AES, ICMA, SBC) received his Bachelor (5-years), Master and the Ph.D. degrees in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), at Porto Alegre, Brazil, in 1992, 1994 and 2001, respectively, and started working with EDA as early as 1989. His graduation project was a symbolic router, which shared an award as one of the two best graduation projects, and was later developed as a master’s dissertation. Between 1994 and 1996 he developed a router tool for the Ágata project, a Brazilian gate-array system for fast prototyping, which would be customized by just configuring the second of two metal layers. As part of the Ph.D. he spent 6 months as a visiting student at UCLA, USA, under the advice of Dr. Andrew Kahng in 1997, where he started to develop a bi-directional heuristic path-search method called LCS*, which is the first algorithm with these properties that can systematically win from a single-source A* search (unidirectional). In 2007, it jointly published the paper with the AMAZE algorithm – Maze routing Steiner trees with effective critical sink optimization, in which the properties of the A* shortest path search are used to generate good Steiner Tree Topologies for multi-pin signal nets, ranging from SMT to MRAs and able to isolate a preferred critical pin for which delay is minimized. From 2012 to 2015, Dr. Johann co-advised student teams that were awarded second and first places in four international research competitions on the subjects of Discrete Gate Sizing and Incremental Timing-driven Detailed Placement. Dr. Johann worked as a professor at the Catholic University of Rio Grande do Sul (PUCRS) from 2000 to 2002 and has been a full-time professor at UFRGS since 2003, having taught a wide range of disciplines in computer science. Dr. Johann co-authored nine book chapters and published more than 70 conference and journal papers, mainly on topics related to Electronic Design Automation. His research interests include algorithms for placement, routing, discrete gate sizing, combinatorial optimization, circuits for audio, recording classical music, and computer music.
Fundamentals and Applications of Modern Single-Photon Detector Circuits and Processing Systems
Abstract: This tutorial will present a comprehensive analysis of single-photon detector sensors and systems. The material will range from semiconductor structure, front-end and readout circuit architectures, to intellectual property. Specifically, we will cover device structures that are configured to yield high-performance single photon detection in CMOS platforms, and we will cover readout circuit architectures that allow complex photon counting applications. We will discuss several high-impact applications including silicon photomultiplier configurations for nuclear imaging/detection and integrated single photon arrays for computer vision. The tutorial has three main educational objectives. The first is to cover the fundamental aspects of single photon detector technology in circuits and systems. The second is to identify the latest research trends in the field. And the third is to situate the technology in the commercial landscape.
Prof Marc Dandin
Carnegie Mellon University
Bio: Marc Dandin received the B.S. and M.S. degrees in electrical engineering and the PhD degree in bioengineering, all from the University of Maryland, College Park, MD, USA. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering at Carnegie Mellon University, Pittsburgh, PA, USA, where he also holds a courtesy appointment in the Biomedical Engineering Department. His current research focuses on integrated circuit design and microsystems development for biomedical applications. He was an Adjunct Professor of electrical engineering at the George Washington University, Washington, DC, USA, where he developed and taught graduate courses in analog and radio-frequency integrated circuit design. He was the Founder and CEO of Kiskeya Microsystems LLC, Rockville, MD, USA, a company developing point-of-care diagnostics technologies for resource-limited settings. He is an intellectual property professional with over ten years of experience in patent preparation and prosecution. He is a senior member of IEEE.
Prof Nicole McFarlane
University of Tennessee
Bio: Nicole McFarlane is an Associate Professor at the University of Tennessee. Her work focuses on circuits and devices for sensing systems. Her research directions includes carbon based nanostructures and CMOS based solutions for biological, environmental, and nuclear science applications. She also works on hardware implemented security solutions and tradeoffs on information and power in mixed signal systems. She currently serves as the Advance Professor in the Tickle College of Engineering for the 2022-2023 academic year. She serves on the Biomedical and Life Science Circuits and Systems and the Sensory Systems Technical Committees as well as the CASS Board of Governors and is an Associate Editor for Transactions on Biomedical Circuits and Systems and an Associate Editor in Chief for Digital Communications for the Open Journal on Circuits and Systems.
Memristive Digital Processing-in-Memory
Abstract: Memristive technologies are candidates to replace conventional memory technologies and storage class memories. They are also widely explored for neuromorphic applications. This tutorial focuses on a different attractive capability of memristors, their ability to perform logic and arithmetic operations using a technique called ‘stateful logic.’ Using stateful logic, data storage and computation can be combined in the memory array to enable a novel non-von Neumann architecture, where both the operations are performed within a memristive Memory Processing Unit (mMPU).
The mMPU relies on adding computing capabilities to the memristive memory cells without changing the basic memory array structure. The use of an mMPU alleviates the primary restriction on performance and energy in von Neumann machine, which is the data transfer between CPU and memory.
This tutorial focuses on the various aspects of mMPU. We start by describing memristors and memristive stateful logic. Then, the mMPU architecture and relevant implications on the computing system and software will be discussed, as well as the examination of the microarchitectural aspects. Examples of applications that can benefit from processing within memristive memory will be shown. Lastly, issues such as design automation and reliability of the mMPU will be presented.
Prof Shahar Kvatinsky
Technion – Israel Institute of Technology
Bio: Shahar Kvatinsky is an Associate Professor at the Andrew and Erna Viterbi Faculty of Electrical and Computer Engineering, Technion – Israel Institute of Technology. Shahar received the B.Sc. degree in Computer Engineering and Applied Physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in Electrical Engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009, he worked as a circuit designer at Intel. From 2014 to 2015, he was a post-doctoral research fellow at Stanford University. Kvatinsky is a member of the Israel Young Academy. He is the head of the Architecture and Circuits Research Center at the Technion, chair of the IEEE Circuits and Systems in Israel, and an editor of Microelectronics Journal and Array. Kvatinsky has been the recipient of numerous awards: the 2021 Norman Seiden Prize for Academic Excellence, the 2020 MDPI Electronics Young Investigator Award, the 2019 Wolf Foundation’s Krill Prize for Excellence in Scientific Research, the 2015 IEEE Guillemin-Cauer Best Paper Award, the 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, an ERC starting grant, the 2017 Pazy Memorial Award, 2014, 2017 and 2021 Hershel Rich Technion Innovation Awards, the 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and seven Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and the design of energy-efficient architectures.
Agile EDA Developments in Memristor Devices, Circuits, Systems, and Manufacturing
Abstract: As the integrated circuit industry enters the post-Moore era, the development direction of chips is gradually shifting from computing performance to energy efficiency. However, in the traditional von Neumann architecture, the process of data transferring between computing units and storage units consumes a lot of energy, limiting the energy efficiency of the chip. Memristor is an emerging non-volatile memory device, which can reduce the transmission overhead between computing and storage units and improving energy efficiency. This provides a new paradigm in “in-memory computing”.
With the rapid increase in the scale of applications (e.g., neural networks) and the continuous innovation of material and fabrication process, memristor-based in-memory computing circuits and systems need to shorten the design cycle to achieve the co-optimization of devices, circuits, and systems. This tutorial presents a new way to further improve the current performance on Electronic Design Automation (EDA) software to handle large scale simulation and optimization problems with memristor devices. We first present the state-of-the-art EDA works in abstraction and optimization methods of memristor device, circuits, and systems. Then, we will present our contributions in these areas.
Prof Yongfu Li
Shanghai Jiaotong University, China
Bio: Yongfu Li (S’09–M’14-SM’18) received the B.Eng. and Ph.D. degrees from the Department of Electrical and Computing Engineering, National University of Singapore (NUS), Singapore.
He is currently an Associate Professor with the Department of Micro and Nano Electronics Engineering and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China. He was a research engineer with NUS, from 2013 to 2014. He was a senior engineer (2014-2016), principal engineer (2016-2018) and member of technical staff (2018-2019) with GLOBALFOUNDRIES, as a Design-to-Manufacturing (DFM) Computer-Aided Design (CAD) research and development engineer. His research interests include analog/mixed signal circuits, data converters, power converters, biomedical signal processing with deep learning technique and DFM circuit automation.
Prof Yuhang Zhang
Pujiang National Laboratory, China
Bio: Yuhang Zhang (S’18) received the B.S. and M.S. degrees in microelectronics from Xidian University, Xi’an, China, in 2014 and 2017, respectively. He has received his Ph.D. degree at Shanghai Jiao Tong University, Shanghai, China, in 2022.
He is currently a research scientist in Pujiang national laboratory. His current research interests include hardware modeling and computer-aided design for emerging non-volatile memory technology.